The present invention relates to a semiconductor memory device, and more particularly, to a method for refreshing data in a dynamic random access memory (DRAM) and a circuit therefor.
Volatile memory devices such as dynamic random access memory (DRAM) require refreshing data stored in the individual memory cells at periodic intervals. Typically, the memory cell of the DRAM comprises an access transistor and a capacitor and the data is expressed as electric charge accumulated in the capacitor. For a variety of reasons the capacitor charge leaks. If the leak is severe enough, data is lost. Therefore, it is necessary to restore the capacitor charge before data is permanently lost. The operation of restoring capacitor charge is called refresh. All of the memory cells included in the semiconductor memory device should be refreshed at least once every refresh period tREF. The refresh operation is divided into a row address signal (RAS) only refresh ROR or self refresh. Where a ROR refresh is desired, the row address is input externally to the semiconductor device. On the other hand, if a self refresh is performed, the row address is internally generated.
FIG. 1 is a diagram of a typical refresh circuit for a DRAM memory cell. Referring to FIG. 1, memory cell 110 comprises access transistor 101 and capacitor 102. The drain of the access transistor 101 is connected to a bit line (BL). The gate of the access transistor 101 is connected to a word line WL. The capacitor 102 is connected between the source of the access transistor 101 and a plate voltage P. As mentioned above, the data is expressed by the amount of charge accumulated in the capacitor 102. A bit line equalizer/precharger 120 includes three NMOS transistors 121, 122, and 123. A bit line sense amplifier 130 includes two cross-coupled PMOS transistors 131 and 132 and two cross-coupled NMOS transistors 133 and 134.
During the refresh operation, the word line is activated to a logic "high" level turning on the access transistor 101. The charge accumulated in the capacitor 102 is distributed to the bit line. Namely, a charge sharing operation is performed by the capacitor 102 changing the bit line capacitance and the voltage level of the bit line BL accordingly. Subsequently, bit line sense amplifier driving signals LAPG and LANG are sequentially activated. When the bit line sense amplifier driving signal LAPG is activated to a logic "low" PMOS transistor 135 is turned on and the signal LA changes to power supply VCC. When the bit line sense amplifier driving signal LANG is activated to a logic "high", signal LAB changes to ground power supply VSS. A voltage difference between the bit line BL and the inverse bit line /BL is amplified by the bit line sense amplifier 130. The amount of charge accumulated in the capacitor 102 is increased by such a bit line sense amplifying operation. Subsequently, the word line and the bit line sense amplifier driving signals are deactivated and a bit line equalizing signal PEQ is activated to a logic "high", precharging the bit line BL and the inverse bit line /BL to a voltage level VBL. The VBL level generally has an intermediate voltage value between the voltage level of logic high or "1" data and the voltage level of logic low data or "0". Also, the bit line BL and the inverse bit line /BL are electrically isolated from the input and output line during the time when the bit line sense amplifying operation is performed. Such a refresh operation is performed at least once every refresh period tREF in order to preserve the data stored in the memory cell.
It takes time to perform a refresh operation on all the memory cells. For example, in a semiconductor memory device which has 1 megabyte capacity and 512 word lines, 512 refresh cycles are required if a single word line is actuated at a time. 256 refresh cycles are required if two word lines are actuated at a time. Therefore, the refresh operation should be performed on as many word lines at one time as possible in order to reduce the number of refresh cycles.
Reducing the number of refresh cycles is particularly important for stably performing the refresh operation and for reducing average power consumption. The refresh operation with respect to one memory cell should be completed within 15.6 .mu.s where 512 refresh cycles are required and the refresh period tREF is 8 ms, while the refresh operation with respect to one memory cell should be completed within 31.2 .mu.s where 256 refresh cycles are required and the refresh period tREF is 8 ms. Since the refresh operation is performed by the word line activating operation, the charge sharing operation, and the bit line sense amplifying operation, as described above, the capacitor charge is not properly restored unless enough time is secured to do so.
Also, the power consumed by the refresh operation can be divided into the power consumed in the memory cell array and the power consumed in the driving circuit for driving the memory cell array. Since all the cells are activated once during the refresh period tREF, the power consumed in the memory cell array is constant. However, since the number of times in which a peripheral circuit for driving the memory cell array is activated for the refresh operation is proportionate to the number of refresh cycles, the power consumed by the peripheral circuit can be reduced by reducing the number of refresh cycles.
Reducing average power consumption has become more important as the use of portable electronic equipment driven by a battery increases. Since most of the power consumed by the semiconductor memory device in sleep mode is consumed by the refresh operation, the refresh operation in sleep mode should be designed to adequately refresh the stored data while minimizing current consumption. The current consumed during the refresh operation can be calculated using the following formula 1. ##EQU1## Where: I.sub.SR-current =average current consumed during the refresh mode;
tREF=refresh period of the semiconductor memory device; PA1 t.sub.ref =actual time in which the refresh operation is performed during one refresh cycle; PA1 N.sub.cycle =number of refresh cycles included in one refresh period; PA1 I.sub.refresh =average current consumed in one tREF; PA1 I.sub.standby =current consumed during standby mode.
As can be gleaned from formula 1, to reduce current I.sub.SR-current it is necessary to either increase tREF or reduce t.sub.ref or N.sub.cycle. The maximum refresh period tREF is typically around 200 ms at 83.degree. C. Thus, tREF can be increased only by a limited amount. There is also a limitation in reducing t.sub.ref since a certain minimum time is required for restoring the charges which have been leaked. Therefore, a method for reducing N.sub.cycle becomes an efficient way of reducing the current and consequent power consumed. I.sub.refresh is not affected by the changes of tREF and t.sub.ref but is affected by the change of N.sub.cycle. This is because the current consumed by the memory cell array and the peripheral circuit are included in I.sub.refresh. When the number of all of the word lines is N.sub.wordline and the number of the word lines in which the refresh operation is performed at one time is N.sub.ref-wl, the number of N.sub.cycles can be calculated using the following formula 2. ##EQU2##
Therefore, N.sub.ref-wl should be increased to reduce N.sub.cycle. When N.sub.ref-wl is increased, the peak current increases since the number of memory cells which are refreshed at one time increases. However, the average current consumed is reduced since the number of refresh cycles decreases.
FIGS. 2A to 2D explain a conventional refresh method for reducing the number of the refresh cycles. In FIGS. 2A to 2D, the memory cell array is constructed by eight blocks. Generally, a plurality of word lines and a plurality of bit lines are included in one block and a memory cell is formed at the intersecting point of the word and bit lines. In FIGS. 2A to 2D, a refresh operation on two blocks is simultaneously performed. Namely, block 0 and block 4 are simultaneously refreshed (FIG. 2A) followed by sequentially and simultaneously refreshing block 1 and block 5 (FIG. 2B), block 2 and block 6 (FIG. 2C), and block 3 and block 7 (FIG. 2D). The refresh operation of one block is not performed at one time with respect to all the memory cells included in the block but is performed in a word line unit. Namely, a predetermined word line is selected among the plurality of word lines included in the block and the refresh operation is performed with respect to the memory cells combined thereto. Then, the refresh operation with respect to the memory cells combined to the next word line is performed. Therefore, the number of refresh cycles required to perform a refresh operation with respect to one block equals the number of the word lines included in the block. For example, where 512 word lines are formed in one block, the number of refresh cycles with respect to one block is 512. Also, where the refresh operation is performed with respect to one block at a time, the required number of refresh cycles is 8.times.512 where 8 blocks exist. Since two blocks are simultaneously refreshed as is shown in FIGS. 2A to 2D, the required number of refresh cycles is reduced by half becoming 4.times.512.
Waveforms for describing the refresh operations with respect to block 0 and block 4 are shown in FIG. 3. The word line WL0.sub.-- 0 included in block 0 and the word line WL4.sub.-- 0 included in block 4 are simultaneously activated and the refresh operation with respect to the memory cells combined thereto is performed. Then, the word line WL0.sub.-- 0 and the word line WL4.sub.-- 0 which were selected are deactivated. The word line WL0.sub.-- 1 included in the block 0 and the word line WL4.sub.-- 1 included in block 4 are activated and the memory cells combined thereto are refreshed. The memory cells combined to the word lines WL0.sub.-- 2 and WL4.sub.-- 2 are refreshed and the rest memory cells are refreshed in the same manner in the next refresh cycle. In FIG. 3, the word lines are sequentially selected, however, the word lines may be selected in a different way. For example, the sequence in which the word lines are selected can be changed using scramble logic. However, more than two word lines included in different blocks are simultaneously activated and the memory cells combined thereto are refreshed in such a case.
As mentioned above, the refresh cycles are reduced in order to stabilize the refresh operation and reduce the average power consumed. Reducing the average consumed power is more critical where the semiconductor memory device is used in a battery operated system. For example, in a battery operated system such as a notebook PC or a laptop computer, it is very important to reduce the average power consumption since the power supplied by the battery is very limited. Therefore, as shown in FIGS. 2A to 2D and 3, it is very important to simultaneously select a plurality of word lines and to perform a refresh operation on the memory cells associated with the selected word lines (hereinafter "a plurality of word lines refresh method") in a volatile semiconductor memory device. However, a disadvantage of using the plurality of word lines refresh method is that peak currents increases as described in FIG. 4.
FIG. 4 shows the respective signal waveforms in one refresh cycle for the plurality of word lines refresh method. Referring to FIG. 4, the bit line and the inverse bit line are precharged to the VBL level before the word lines are selected. In such a state, a plurality of word lines WL0.sub.-- 0 and WL4.sub.-- 0 are selected and are activated to a logic "high" level. When the word line is activated, the access transistors of the memory cells combined thereto are turned on and the voltage levels of the bit line and the inverse bit line change according to the data stored in the memory cell. The bit line sense amplifier enable signals PS and PSD are activated to a logic "high" level, amplifying the voltage difference between the bit line BL and the inverse bit line /BL. The bit line sense amplifier enable signals PS and PSD have identical waveforms regardless of the word line selected. Namely, the bit line sense amplifying operations in all the bit lines and inverse bit lines included in the selected block are simultaneously activated. Thus, the power current I.sub.CC and the earth current I.sub.SS instantaneously increase as shown in FIG. 4. The peak value of the power current I.sub.CC and the earth current I.sub.SS increase as the number of the word lines activated at a single time increases. In other words, as the number of the blocks selected at one time increases, the peak current increases. Here, BL0 and /BL0 respectively denote the signal waveforms of the bit lines and the inverse bit lines included in block 0 and BL4 and /BL4 respectively denote the signal waveforms of the bit lines and the inverse bit lines included in block 4. In a battery powered system, the battery is damaged when the peak current increases. As a result, the system may not operate properly generating otherwise avoidable system errors. The system may also fail because the current supplied by the battery is limited. Therefore, it is necessary to lower the peak current drawn by the system. One proposed solution has been to increase the number of the word lines selected within a block to reduce the average power consumption and to stabilize the refresh operation. However, as the number of the selected word lines increases, the peak current is increased.